43 lines
1.6 KiB
TeX
43 lines
1.6 KiB
TeX
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\section{Experience}
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\outerlist{
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\entrybig
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{\textbf{PRODAFT}}{\textit{ Den Haag, NL }}
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{\textit{ Developer \& Offensive Cyber Threat Intelligence Analyst }}{\textit{ September 2022 - Present }}
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\innerlist{
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\entry{Working on a threat intelligence correlation platform (CRADLE) to aggregate artifacts from data sources with high throughput.}
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\entry{Development and implementation of graph-based algorithms using Neo4J: PageRank, Recommendation, Explainable AI, Risk Prediction.}
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\entry{Internal tool development for automating TI tasks, management of team members and collaborative knowledge management.}
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\entry{Proactive threat hunting and penetration testing}
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}
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\vspace{0.2em}
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\entrybig
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{\textbf{Rotterdam Police Department}}{\textit{ Rotterdam, NL }}
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{\textit{ Intern at Team Zeden and TBKK }}{\textit{ April 2023 - July 2023 }}
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\innerlist{
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\entry{Worked on the development of an internal tool used for detection of encrypted containers in a live system or forensic evidence files.}
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}
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\vspace{0.2em}
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\entrybig
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{\textbf{TU Delft}}{\textit{ Delft, NL }}
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{\textit{ Teaching Assistant }}{\textit{ September 2022 - February 2024 }}
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\innerlist{
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\entry{Assisted in the teaching of the courses Object Oriented Programming, Computer Organization, Web \& Database Technologies and Embedded Software.}
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}
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\vspace{0.2em}
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\entrybig
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{\textbf{ASELSAN}}{\textit{ Ankara, TR }}
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{\textit{ Intern at Software and Hardware Design }}{\textit{ January 2020 - February 2020 }}
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\innerlist{
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\entry{Designed and produced a simple timing circuit \\ Learned the basics of FPGA design and developed a simple FPGA project using VHDL. }
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}
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}
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